///////////////////
//////Designer Duping
//////description 8channel 125k tester top file


module test_top(
	//input
	clk_in,//FPGA system clock input
	rst_n_top,//reset signal
	rxd_ul,//
	man_i, //Manchester code input 
    test_mode,
	
	//output 
	txd_ul,
	// sram_ctrl_addr_de2, //debug the procedue
	sram_ctrl_addr,
	n_sram_we,//to sram in fpga
	n_sram_ce,//to sram in fpga
	n_sram_oe,//to sram in fpga
	n_sram_lb,//to sram in fpga
	n_sram_ub,//to sram in fpga
	clk_125k_o,
	led,
	// clk_1m,
	// clk_250k,
	//rxd_fliter,
	oe_8ch,
	// end_flag,
    data,
    data_val,
    
	//inout
	sram_dq//to sram in fpga
	
);
parameter N =  8;	
input clk_in;
input rst_n_top;
input rxd_ul;
input [7:0] man_i;
input test_mode;

output txd_ul;
// output [19:0] sram_ctrl_addr_de2;
output [17:0] sram_ctrl_addr;
output n_sram_we,
       n_sram_ce,
	   n_sram_oe,
	   n_sram_lb,
	   n_sram_ub;
output [7:0]  clk_125k_o;
output [3:0]  led;
// output clk_1m,
       // clk_250k;
//output [7:0] rxd_fliter;
output [7:0] oe_8ch;
// output [7:0] end_flag;
output [7:0] data,
             data_val;

inout [15:0]sram_dq;	
   
wire clk_1m;
wire clk_250k;
wire rst_n;
wire clk_125k;
wire down_link_req;
wire up_link_req;

wire up_sram_rd,
	 up_sram_wr;
wire [12:0] up_sram_addr;
wire down_sram_rd,
	 down_sram_wr;
wire [12:0]down_sram_addr;
wire [7:0]man_i;
wire sram_ack,
	 sram_busy;
wire [7:0] sram_data_out;//data form sram_ctrl
wire [7:0] up_sram_data;
wire [N-1:0] sram_data_in;
wire rd,
	 wr;
wire [12:0] addr_in;
wire [7:0] down_sram_data;
//wire down_wr_sram_req;
wire sram_mux;
wire [17:0]sram_ctrl_addr;
wire [1:0] ch_125k_en;

reg  [7:0] clk_125k_o ;


always@(*)
  if(&ch_125k_en)
        clk_125k_o = {clk_125k,clk_125k,clk_125k,clk_125k,clk_125k,clk_125k, clk_125k,clk_125k};
  else if(ch_125k_en[0]) 
        clk_125k_o = {1'b0,1'b0,1'b0,1'b0,clk_125k,clk_125k,clk_125k,clk_125k};
  else if(ch_125k_en[1])
        clk_125k_o = {clk_125k,clk_125k,clk_125k,clk_125k,1'b0,1'b0,1'b0,1'b0};
  else 
        clk_125k_o = {1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0};               
  

// assign  clk_125k_o  = (&ch_125k_en) ? ({clk_125k,clk_125k,
                                        // clk_125k,clk_125k,
                                        // clk_125k,clk_125k,
                                        // clk_125k,clk_125k}) : (
        // ch_125k_en[0] ?  {clk_125k,clk_125k,
                          // clk_125k,clk_125k,
                           // 1'b0,1'b0,
                           // 1'b0,1'b0} :
        // (ch_125k_en[1] ? {}  :  8'd0));

                
       
  
                
//assign  sram_ctrl_addr_de2   =  {1'b0,1'b0,sram_ctrl_addr};
clk_rst_gen clk_rst_clock(
					//input
					.clk_in(clk_in),
					.arst_n(rst_n_top),
					//output
					.sys_rst_n(rst_n),
					.clk_125k(clk_125k),
					.clk_250k(clk_250k),
					.clk_1m(clk_1m)

); 

up_link_top up_link_ins (
					.clk(clk_1m),
					.nrst_ul(rst_n),
					.down_link_req(down_link_req),
					//a_o_addr,
					.ack(sram_ack),
					.rxd_ul(rxd_ul),
					.data_tx(sram_data_out),
					//output
					.up_link_req(up_link_req),
					.error_uu(),
					.s_o_addr(),////this is a uncertain pin
					.rd(up_sram_rd),
					.wr(up_sram_wr),
					.addr(up_sram_addr),
					.txd(txd_ul),/**********///this is a uncertain pin
					.data_rx(up_sram_data),//**********///this is a uncertain pin
					.led(led)
);

down_link_top down_link_ins(
		//input
		.clk_1m(clk_1m),
		.clk_250k(clk_250k),
		.rst_n(rst_n),
		.up_link_req(up_link_req),
		.async_rxd(man_i),
		.sram_ack(sram_ack),
		.sram_busy(sram_busy),
		.sram_data_out(sram_data_out),//data read from sram ctrl
		.test_mode(test_mode),
		//output 
		.down_link_req(down_link_req),
		.down_sram_wr(down_sram_wr),
		.down_sram_rd(down_sram_rd),
		.down_sram_addr(down_sram_addr),
		.down_sram_data(down_sram_data),//data write to the sram
		.sram_mux(sram_mux),
		.rxd_fliter(rxd_fliter),
		.oe_8ch(oe_8ch),
        .ch_125k_en(ch_125k_en),
        .data(data),
        .data_val(data_val)
        
);



sram_mux sram_mux_ins(
	//input
	.clk_1m(clk_1m),
	.rst_n(rst_n),
	.down_link_req(down_link_req),
	.up_link_req(up_link_req),
	.sram_mux(sram_mux),
	//sram_data,
	.sram_ack(sram_ack),
	.down_sram_wr(down_sram_wr),
	.down_sram_rd(down_sram_rd),
	.down_sram_addr(down_sram_addr),
	.down_sram_data(down_sram_data),
	//.down_wr_sram_req(down_wr_sram_req),
	.up_sram_wr(up_sram_wr),
	.up_sram_rd(up_sram_rd),
	.up_sram_addr(up_sram_addr),
	.up_sram_data(up_sram_data),
	
	//output
	.sram_rd(rd),
	.sram_wr(wr),
	.sram_addr(addr_in),
	.sram_data_out(sram_data_in)
);






sram_ctrl sram_ctrl_ins(
		//input
		  .clk_1m(clk_1m),
		  .rst_n(rst_n),
		  .wr(wr),
		  .rd(rd),
		  .addr_in(addr_in),
		  .sram_oe(1'b1),
		  .sram_data_in(sram_data_in),
		  //output
		  .sram_ctrl_addr(sram_ctrl_addr),///to sram in fpga
		  .data_out(sram_data_out),
		  .ack(sram_ack),
		  .busy(sram_busy),
		  .n_sram_we(n_sram_we),//to sram in fpga
		  .n_sram_ce(n_sram_ce),//to sram in fpga
		  .n_sram_oe(n_sram_oe),//to sram in fpga
		  .n_sram_lb(n_sram_lb),//to sram in fpga
		  .n_sram_ub(n_sram_ub),//to sram in fpga
		  //inout
		  .sram_dq(sram_dq)////to sram in fpga
);

endmodule 